Functional Hardware Verification

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Description

How to Verify Chips and Eliminate Bugs

When developing chips it is essential that they get verified thoroughly because it is very hard or impossible to fix them once they have…

Class Summary

When developing chips it is essential that they get verified thoroughly because it is very hard or impossible to fix them once they have been manufactured. In this class, you will learn how to program verification environments that verify chip functionality efficiently, as well as understand and leverage automation such as constrained random test generation and improve code reuse leveraging a standardized methodology.

What Should I Know?

Programming experience including object-oriented programming. Da…

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How to Verify Chips and Eliminate Bugs

When developing chips it is essential that they get verified thoroughly because it is very hard or impossible to fix them once they have…

Class Summary

When developing chips it is essential that they get verified thoroughly because it is very hard or impossible to fix them once they have been manufactured. In this class, you will learn how to program verification environments that verify chip functionality efficiently, as well as understand and leverage automation such as constrained random test generation and improve code reuse leveraging a standardized methodology.

What Should I Know?

Programming experience including object-oriented programming. Data & Control structure.

This course is developed by Cadence Design Systems, a global leader in electronic design automation. Cadence® software, hardware, IP, and services help customers around the world to overcome a range of technical and economic hurdles.

What Will I Learn?

This course will teach you how to think like a verification engineer. It will show the software development aspects you need to know to ensure chips are working as expected. You will learn how to implement verification environments.

Course Instructors

Axel Scherer Instructor

Axel Scherer is a senior engineer and manager with over 10 years of experience building new markets and innovating technical products. Currently, Axel is leading a team for Testbenches and Verification Methodologies in the Functional Verification R&D group at Cadence Design Systems, a leading global Electronic Design Automation company. Axel's work centers on advanced verification on various technologies spanning formal equivalence checking, model checking, assertion-based verification and test bench simulation. He is a passionate and innovative leader with a proven track record of motivating and enabling global teams to succeed.

Hannes Fröhlich Instructor

Hannes Fröhlich is a member of the Product Expert Team in the Functional Verification R&D group of Cadence Design Systems, a leading global Electronic Design Automation company. Hannes' primary focus area is the Specman/e and UVM Multi-language solution. He has over 10 years of verification experience spanning from an AE to AE Manager to Solutions Architect. He has been involved with assisting customers implementing Specman/e technology around the globe, and his expertise has enabled hundreds of successful projects.

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There are no frequently asked questions yet. Send an Email to info@springest.com